Grovf is seeking a skilled Senior ASIC Digital Design Engineer to join our R&D team in Yerevan, Armenia. Our work environment is dynamic, educational, and challenging, offering employees the opportunity to contribute to the development of next-generation networking devices for Next generation AI Infrastructure that lead the industry in performance and power efficiency. As part of the team, you will be involved in all stages of ASIC development, including Micro-Architecture, Design, and Verification. Our collaborative environment fosters growth, innovation, and leadership, offering the opportunity to work alongside industry experts and contribute to groundbreaking advancements.At Grovf, every individual plays a vital role in the company's success. If you're looking for a rewarding career, talented colleagues, and a great environment that fosters growth, challenges, and leadership, Grovf is the place for you.

Key Responsibilities

• Develop server-grade SoC RTL

• Integrate various IPs (PCIe, DDR, UCIe) into the SoC system

• Collaborate with cross-functional teams (Software, Hardware, Verification) to ensure high-quality product delivery

Required Qualifications

• B.Sc. / M.Sc. in Computer Engineering, Electrical Engineering, or a related field
• 4+ years of proven experience in RTL Front-End ASIC Design or Verification (ASIC Design)
• Strong proficiency in English
• Experience in SoC front-end ASIC RTL digital logic design using Verilog or SystemVerilog
• Hands-on experience across all aspects of the ASIC development process, including front-end tools and methodologies
• Ability to write specifications and translate them into designs
• Experience with multiple clock domains and asynchronous interfaces
• Familiarity with front-end implementation tasks such as synthesis, timing, area/power analysis, linting, and logic equivalence checks
• Understanding of low-power design techniques, such as clock- and power-gating, is an advantage
• Strong communication skills across all internal teams
• Familiarity with scripting languages (Perl, Python, or Tcl) is a plus
• Experience with common on-chip bus protocols (e.g., AMBA - AXI, AHB, APB) is a plus
• Understanding of software and operating concepts is a bonus

Preferred Skills
 

• Knowledge of security concepts is a bonus

• Understanding of software and operating concepts is a bonus

• Knowledge of system architecture, CPU & IP Integration, and power/clock management is a plus

Ways to Stand Out
 

• Demonstrated ability to mentor and guide engineers

• Proactive attitude towards team collaboration and knowledge-sharing