Design for Test Engineer

Uhnder

Austin, TX, US
  • Job Type: Full-Time
  • Function: Engineering QA
  • Post Date: 06/09/2021
  • Website: www.uhnder.com
  • Company Address: 3409 Executive Center Drive, Suite 205, Austin, TX, 78731

About Uhnder

Uhnder develops disruptive products for sensing, cognition, and communication.

Job Description

Summary/Objective

Uhnder has developed the world’s first automotive digital Radar on Chip (RoC).  Sensors based on Uhnder’s Digitally Coded Modulation (DCM) technology achieves new and unprecedented levels of performance for advanced driver assistance systems (ADAS) and autonomous driving solutions.  Founded in 2015, its main engineering operations center is in Austin, Texas, USA with design facilities in India and China.

As a Design-for-Test Engineer, you will join a team of industry experts spanning mixed-signal, RF, digital, systems and software experts to develop the next generation of electronics surrounding us and impacting us in our everyday lives.   You will focus on the implementation of the RoC chips with an emphasis on all aspects of the Design-for-Test, from concept to production silicon, including: specification, architectural development, fault modeling, and simulation, test coverage analysis, and overall test coverage improvement.

Essential Functions

  • Implement and validate various DFT architectures and features like hierarchical SCAN, and MBIST.
  • Implementation of in-field test features like LBIST and on-demand MBIST.
  • Perform ATPG pattern generation and simulation.
  • Perform coverage analysis to meet stringent test coverage requirements.
  • Perform Gate level SDF based simulations and debugging.
  • Develop efficient DFT flows.
  • Work closely with Physical Design team to develop and validate DFT timing constraints and timing modes.
  • Participate in silicon bring and validation on ATE test, and system during post tape-out phase of the project.

Required Education and Experience:

  • BS in Electrical Engineering, MS preferred.
  • 5 or more years of relevant industry experience.
  • Knowledge in Boundary Scan, JTAG, MBIST, LBIST, and Scan Compression.
  • Strong understanding of core-based test methodology and scan isolation.
  • Experience in SCAN/MBIST silicon bring-up, validation, and debug on ATE tester.
  • Strong scripting skills in Tcl, Perl, or Python.
  • Good communication skills.
  • Experience with Cadence’s Genus and Modus tools is a plus.

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Disclaimer: Local Candidates Only
This company does NOT accept candidates from outside recruiting firms. Agency contacts are not welcome.