Advanced Packaging Engineers

Fathom Computing

Union City, CA, US
  • Job Type: Full-Time
  • Function: Operations
  • Post Date: 02/14/2021
  • Website:
  • Company Address: 380 Portage Ave, Palo Alto, CA, 94306

About Fathom Computing

Fathom Computing is building optics-based hardware to run artificial intelligence with unprecedented performance.

Job Description

Fathom Radiant is building computer hardware to train neural networks at the human brain-scale and beyond. By combining the complementary strengths of optics and electronics, we have developed a revolutionary interconnect fabric that enables a flexible machine with the network capacity of a supercomputer and unprecedented scalability. Help us construct the future of machine intelligence. Our founding team has previously founded startups with more than $500 million in exits. We are well-funded from investors including Khosla Ventures, Jeff Bezos, and many others.
We’re seeking to fill multiple Packaging roles covering standard IC packaging, thermal management, and advanced packaging (e.g. 2.5 and 3D integration). Candidates with domain expertise in one or multiple of these areas are encouraged to apply. The scope of the roles will be determined by the background of the persons hired. As an Advanced Packaging Engineer at Fathom Radiant you will solve interdisciplinary packaging challenges, collaborating closely with colleagues from other disciplines (epitaxy, optoelectronics fabrication, optics, IC design, systems integration) to enable novel optoelectronic hardware for machine learning.

Areas of Contribution

      • Develop packaging designs to support and address digital interfaces, power integrity, and thermal considerations while not sacrificing optical performance. This potentially includes initial design concept, thermal, mechanical, and electrical (DC and RF) analysis and optimization, and manufacturing feasibility at die, substrate and assembly level
      • Design high performance substrates for signal and power distribution, mechanical stability, and thermal management
      • Manage thin film stresses, CTE mismatch, thermal and mechanical cycling, vibration and other environmental stressors
      • Develop advanced 2.5D and 3D microelectronic packaging solutions for next generation digital, mixed-signal, and analog silicon CMOS electronics with integrated III-V (GaAs, InP, GaN) components
      • Develop packaging designs and manufacturing process flows to allow DBI, microbumping, BGA, LGA and/or other integration technologies for wafer-to-wafer and chip-to-wafer stacks.
      • Assist with the documentation for product components, including models, production drawings, inspection criteria, etc.
      • Manage and collaborate with contract manufacturers for specification, fabrication and evaluation of the design and manufacturing processes
      • Evaluate designs for manufacturability and reliability; oversee metrology and failure analysis of packaging components
      • Some travel (<10%) may be required


    • BS, MS or PhD in electrical engineering, physics, materials science or related discipline, or equivalent experience, required
    • Minimum of 5 years of relevant experience in ASIC/GPU/CPU or optoelectronics packaging, substrate design, 2.5D and 3D microelectronics packaging, and/or thermal and mechanical package design
    • Experience with wafer and chip integration technologies, from mainstream (BGA, LGA) to state-of-the-art (microbump, DBI)
    • Knowledge of multi-physics simulation tools (ANSYS, COMSOL), high frequency and electromagnetic simulation tools (ADS, ANSYS HFSS), and 3D CAD mechanical drawing environment. 
    • Experience with Cadence SiP Layout
    • Knowledge of basic statistical process control and/or design of experiments principles. 
    • Expertise in production packaging design, having previously transferred designs to manufacturing
    • Working knowledge of microelectronic packaging test equipment
    • Experience in thermal, mechanical, electrical and environmental characterization and reliability testing; familiarity with failure analysis and package qualification. 


      • Familiarity with nano/microelectronics semiconductor fabrication and back end of line (BEOL) processing. 
      • Working knowledge of signal requirements for multi-bit busses, such as DDR4/3, and high-speed serial interfaces such as PCIe-gen4/3
      • Lab experience with high speed electrical measurements and test equipment
      • Experience developing in-line packaging test equipment
      • Experience with Computational Fluid Dynamics software tools, preferably with a background in modeling + experimental analysis
      • Cadence SiP Layout Advanced WLP Option and Cadence Allegro
We highly encourage submission of a cover letter, just tell us why you're here :)

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Disclaimer: Local Candidates Only
This company does NOT accept candidates from outside recruiting firms. Agency contacts are not welcome.