Digital Verification Engineer, CH, UK

Kandou Bus

Lausanne, CH
  • Job Type: Full-Time
  • Function: Engineering Hardware
  • Post Date: 02/19/2021
  • Website: www.kandou.com
  • Company Address:

About Kandou Bus

Developer of a SerDes IP and chip serial links designed to provide enhanced communications between chips inside electronic systems. The company's chip links increase the bit-rate and the reach for given physical communication and reduces the power consumption, enabling users to get compute power in a smaller form factor, at a lower cost and less energy consumption.

Job Description

At Kandou, we are a team of passionate professionals striving to make a mark in the trajectory of the semiconductor industry. If you love to be part of a start-up that is challenging established tech giants and you are a proactive problem-solver who is motivated by pushing your limits and challenging the status quo, we have an opportunity for you.

 

Kandou is actively seeking a resourceful Digital Verification Engineer (Serdes) ideally for our office either Lausanne (Switzerland) or UK.

 

Key responsibilities

 

  • Work with Design Engineers in verification and validation of circuit designs
  • Prepare design verification plan based on design specifications
  • Plan and schedule assigned projects for timely completion
  • Utilize latest techniques, tools and technologies for design verification activities
  • Maintain design verification environment, track and close design bugs
  • Develop design verification methodologies and implement standard debug flows
  • Participate in design reviews

 

 Your profile

 

  • 5+ years’ experience in the semiconductor industry.
  • Expert in digital design verification, using standardized methodologies, i.e. UVM
  • Experience in simulating mixed signal designs with real-number Verilog behavioural models is highly desirable
  • Familiarity with SerDes is highly desirable
  • Experience with SystemVerilog Assertions (SVA) and formal verification is valuable
  • Experience in constrained random testbench development
  • Proven track record in verifying complex designs (preferably in high volume ASIC applications)
  • Experience with 3rd party VIP usage is an added bonus
  • Familiarity with high level protocols (e.g. PCIe, USB, DP) is an added bonus
  • Bachelor of Engineering in Electronics and Electrical Engineer (equivalent or higher)

 

Competencies

  • Very good knowledge on Metric driven verification including test planning and coverage closure
  • Very good knowledge on simulation tools and debugging techniques
  • Knowledge of Cadence simulation tools is an added bonus
  • Good scripting techniques, regression setup and regression management
  • Good understanding of simulation and verification environments
  • Skilled in trade-offs between quality and schedule
  • Excellent team player with great communication skills, proactive and self-reliant
  • Be rigorous and have an analytical mind

 

If you recognise yourself in the description above, and love to be part of a growing Company, are a good team player with an upbeat approach to life, we would love to hear from you. 

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Disclaimer: Local Candidates Only
This company does NOT accept candidates from outside recruiting firms. Agency contacts are not welcome.