- Job Type: Full-Time
- Function: Engineering Hardware
- Post Date: 03/28/2021
- Website: www.nextsilicon.com
- Company Address:
About NextSilicon
NextSilicon brings together top talent in the areas of computing, business operations, and product design, management, and marketing. Our R&D team is comprised of individuals at the top of their fields who have outstanding records in chip design and software development. We are committed to building a work environment that is fun, inclusive, and provides equal opportunities for everyone, because we believe this leads to happy and productive employees.
Job Description
NextSilicon is looking for a talented and experienced engineer to participate in the physical design activities of the company’s product. This position involves working with external backend vendors as well as carrying out critical tasks in-house, and leading aggressive backend methods to meet challenging targets in terms of area, timing, and layout. In this role, you will be at the center of the company’s design efforts and will have a significant influence on product architecture.
Key qualifications
10+ years of physical design experience, leading complex process designs
In-depth knowledge of process considerations and circuit aspects
Knowledge of physical design industry standards and practices, including physically aware synthesis, floor-planning, and place and route
Experience developing and implementing power-grid and clock specifications
Solid understanding of all aspects of physical construction, integration, and physical verification
Good command of industry standard physical design and synthesis tools
Understanding of scripting languages such as Perl/Tcl
Working knowledge of extraction and STA methodologies and tools
Good understanding of physical design verification methodology for debugging LVS/DRC issues at chip/block level
Proficiency in power delivery, signal integrity, advanced packaging, power projection, and design for low dynamic power
Master’s degree in electrical engineering or computer science, and/or equivalent experience
Responsibilities
Generate and analyze critical block/chip-level static timing constraints
Spec and define full chip floor-plan including pin placement, partitions, and power grid
Develop and validate high-performance low power clock network guidelines
Perform critical block-level place and route and make design decisions that meet timing, area, and power constraints
Review the vendors’ physical design verification flow at chip/block level and provide guidelines to other designers on how to fix LVS/DRC violations
Work with vendors on defining physical design methodologies and assist in flow development for chip integration
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