Sr, ASIC Verification Engr

Infinera Corporation

Bangalore, IN
  • Job Type: Full-Time
  • Function: Engineering QA
  • Post Date: 01/14/2021
  • Website:
  • Company Address: 169 Java Drive, Sunnyvale, CA, 94089

About Infinera Corporation

Infinera empowers network operators to scale network bandwidth, accelerate service innovation and automate optical network operations. Service providers, cloud operators, governments and enterprises across the globe rely on Infinera Intelligent Transport Networks to enable services that create rich end-user experiences based on efficient, high-bandwidth optical networking.

Job Description

Infinera provides the Network Connectivity Solutions for the World’s most demanding Networks. As an Infinera employee, you will be solving the industry’s toughest problems by leading, not following. Collaborate across our diverse culture, global reach and reap its benefits.

Job description

As a member of the verification team working on IPs and Full Chip candidate will
• Take ownership of  verification activities at IP or Sub-chip Level
• Lead a team of verification engineers to scope, architect, plan, execute and close verification at IP or Sub-chip level
• Develop verification infrastructure consisting of drivers, checkers, verification IPs/components, base classes and tests, scoreboards in system-verilog environment from scratch for IPs and sub-chips.
• Develop test plans at IP, sub-chip/cluster and Full Chip level
• Code Tests  and debug
• Develop coverage plan and execute to meet functional and code coverage goals
• Participate in reviews, explore and experiment with new verification methodologies
• Plan, Develop, Execute and Close - lab validation of sub-systems using infrastructure consisting of scripts and  tests - for chip bring up and debug

Requirements :

1. Candidate must have a Bachelor's Degree or higher in CS or EE with very good academics. Masters degree preferred.
2. 5+ years’ experience in ASIC/FPGA Verification.
3. Strong Verilog, SystemVerilog, C/C++, and Perl/Python/shell scripts programming skills.
4. Knowledge of SystemVerilog/VMM/OVM/UVM verification methodologies; experience with code coverage, functional coverage, formal verification tools.
5. Participation in a recent multi-million gate ASICs verification in telecom/networking area is preferred
6. Should have prior experience with scoping, planning, architecting, executing and closing verification activities at IP/Sub-chip or at chip level
7. Knowledge of networking standards such as SONET (OR) OTN/G.709 and Layer 2/3 networking protocols is desired 8. Networking and packet based protocol experience is desired

If there are exceptional candidates, some of the requirements can be diluted.

Recruiter Tag: #LI-SN1

Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, religion, color, national origin, sex, age, status as a protected veteran, or status as a qualified individual with disability. EEO Employer/Vet/Disabled.

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Disclaimer: Local Candidates Only
This company does NOT accept candidates from outside recruiting firms. Agency contacts are not welcome.