Serdes Analog Architect, CH, UK

Kandou Bus

Lausanne, CH
  • Job Type: Full-Time
  • Function: Engineering Hardware
  • Post Date: 01/07/2021
  • Website: www.kandou.com
  • Company Address:

About Kandou Bus

Developer of a SerDes IP and chip serial links designed to provide enhanced communications between chips inside electronic systems. The company's chip links increase the bit-rate and the reach for given physical communication and reduces the power consumption, enabling users to get compute power in a smaller form factor, at a lower cost and less energy consumption.

Job Description

At Kandou, we are a team of passionate professionals striving to make a mark in the trajectory of the semiconductor industry. If you love to be part of a start-up that is challenging established tech giants and you are a proactive problem-solver, able to multitask in a high energy environment and someone who is motivated by pushing their limits and challenging the status quo, we have just the opportunity for you.

We are actively seeking a resourceful Chip Architect Analog for our office in Lausanne (CH) or Northampton/Reading (UK).

Key responsibilities

  • Write and own content of analog specifications at chip, block and interface level.
  • Specify block level requirements (jitter budget, power budget, etc.) to achieve system requirements at the chip level.
  • Working closely with analog, digital and verification teams to ensure design meets analog architecture specifications including review and sign-off authority regarding deviations from specification.
  • Participate in standards bodies and represent company interests in those bodies.
  • Responsibility for analog design and debug of assigned analog blocks (when appropriate).
  • Work on cross-functional teams to implement improvement actions to optimise design cost, quality and /or schedule as appropriate.

Your profile

  • Bachelor of Engineering in Electronics and Electrical Engineering (equivalent or higher).
  • 10+ years of experience in the semiconductor industry.
  • 5+ years of experience in Serdes architecture and design.
  • Proven experience with high speed Serdes analog design, system architectures, and ecosystems.
  • Proven experience with decomposing and partitioning specifications between analog and digital domains, and within analog domains to optimize design architecture.
  • Experience writing specifications at the chip and block levels and writing interface specifications for interfaces external and internal to the chip.
  • Experience in leading and working with teams across different geographical sites.
  • Experience with representing the design team and presenting to customers.

 

 Competencies

  • Familiarity with Serdes architectures and associated analog circuits, including Receiver architectures, Transmitter architectures, and Phase-Locked Loop designs.
  • Proficient at partitioning chip level requirements to specifications at the block level.
  • Knowledge of digital and analog design flows.
  • Proficient at analog design using Cadence tools.
  • Proficient debug skills to identify bugs in analog architecture, functionality and performance.
  • Demonstrated team building and leadership skills, including working with cross-functional teams.
  • Must possess strong communication skills including the ability to write specifications and internal/external presentations.

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Disclaimer: Local Candidates Only
This company does NOT accept candidates from outside recruiting firms. Agency contacts are not welcome.