Career | Senior Design Verification Engineer | Grovf

Senior Design Verification Engineer


Yerevan, AM

  • Job Type: Full-Time
  • Function: Engineering QA
  • Industry: Enterprise/B2B Software
  • Post Date: 11/24/2022
  • Website:
  • Company Address: 2150 Shattuck Ave, Penthouse, Berkeley, California 94704-1347, US

About Grovf

Accelerating Big Data Analytics

Job Description

The ASIC Verification Engineer's primary job function is Pre-Silicon Design Verification of Network processor accelerator IPs and SOC designs using industry-standard verification methodologies. To perform this job successfully, an individual must be able to perform each essential duty satisfactorily.

Below are listed the knowledge, skills, and abilities required.

  • BS/MS in Electrical Engineering or related degree or certification required.
  • 5+ years of experience in System Verilog or UVM based verification
  • Good skills in verification methodology, test planning, and test bench architecture
  • Very good experience with System Verilog and advanced verification techniques: constrained random verification, code/functional/assertion coverage.
  • Experience in integrating Verification IPs, and HW/SW Co-Simulation is a plus.
  • Knowledge of RISC-V-based SoC architecture and system busses (AHB, AXI, CHI) is strongly desired.
  • Knowledge of standard SoC interfaces and high-speed IO protocols (PCIe, DDR, Ethernet) is a plus.
  • Programming skills in C++, Python, and shell scripting are desired.

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