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| Principal RTL Design Engineer | | Quartics | | | Senior RTL design engineer to be responsible to design and verify Video related ASIC RTL block. May also be responsible for some RTL design work involved at the SOC level such as Arm interfaces, AHB/AXI bus structures and peripherals such as DDR2/3, PCIe, SATA, USB, 2d/3d graphics, encryption, etc | 10+ years of RTL design experience
· Developed SOC designs using Verilog/VHDL
· Developed ASIC RTL blocks from scratch using Verilog/VHDL
· Experience with Arm based SOC designs
· Experience in Video codecs
· Worked with Perl, Verilog, C, system Verilog
· Run vcs simulations at gate level.
· Familiar with chip bring up
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